1. Field of the Invention
The present invention relates to a probe card for testing semiconductor integrated circuits and also to a method of probe-testing semiconductor integrated circuits by using the probe card.
2. Description of the Related Art
Probing test is performed on semiconductor integrated circuits for their electrical characteristics. The test is carried out after the wafer process and before the dicing process, namely after the integrated circuits have been formed in a semiconductor wafer, arranged in rows and columns. By this test it is determined whether the integrated circuits are defective or not. Any integrated circuit found defective is not subjected to an assembly step. This helps to prevent an unnecessary increase in the manufacturing cost of semiconductor devices.
The integration density of semiconductor integrated circuits (ICs) has much increased in recent years. Because of the increased integration density, the time of testing each integrated circuit, or each IC chip (hereinafter called “chip”), has increased. Until recently the probing test has been performed, chip by chip. At present a plurality of chips are tested simultaneously, in order to shorten the time of testing one chip.
FIG. 1 is a perspective view, illustrating a conventional probe card 5 and a semiconductor wafer 1. As FIG. 1 shows, 84 chips 3 are arranged in rows and columns on the semiconductor wafer 1. The probe card 5 has one probe-needle hole 7. Protruding through the hole 7 are four groups 9a, 9b, 9c an 9d of needles to test four chips 3a, 3b, 3c and 3d. Thus, the probe card 5 is used to test four chips at the same time, for determining the electrical characteristics of the chips.
The integration density of semiconductor integrated circuits, particularly semiconductor memories, is still increasing. The time for testing one chip inevitably increases even if the probe card 5 (FIG. 1) is used. In order to shorten the time, it is necessary to provide more groups of prove  probe needles for each column so that the card 5 may test more chips at the same time.
FIG. 2 is a perspective view, showing another type of a conventional probe card 5′ and a semiconductor wafer 1. As seen from FIG. 2, the probe card 5′ has eight groups 9a to 9h of needles, which protrude through a hole 7. The groups 9a to 9h of needles are provided to test eight chips 3a to 3h at the same time, whereas the four groups 9a to 9d of needles of the probe card 5 (FIG. 1) are used to test four chips 3a to 3d simultaneously. Hence, the probe card 5′ helps to shorten the time required for testing one chip.
When the probe card 5′ was used to accomplish a probing test, however, more chips were likely found  to be found defective than in the case where the probe card 5 shown in FIG. 1 was used. To determine whether this tendency is  was genuine or not, the chips tested by using the card 5′ were tested, one by one. Of the chips which were found defective when tested by means of the  using card 5′, some proved flawless. This means that the probe card 5′ can test chips but with an insufficient accuracy.
Some reasons for the insufficient test accuracy, that are conceivable at present, will be discussed below.
The response signals output from all chips simultaneously tested are supplied at the same time to the tester via the probe card 5′. The tester compares the levels, leading edge time and trailing edge time of the response signals with prescribed values or ranges, determining whether the chips are flawless or not.
The probe needles of the groups 9a to 9h are connected to probe contacts 11 provided on the circumferential edge of the probe card 5′ by wires (not shown) which are provided within the card 5′. It is at the probe contacts 11 that the probe card 5′ can contact a tester. The response signal from each chip tested has its level lowered before reaching the tester, because of the resistance of the wire provided in the card 5′. It is natural that the leading and trailing edge time of the response signal shift in accordance with the capacitance of the wire.
The more groups of probe needles provided to test more chips at a time, the greater the diameter D of the probe card 5′. As the the diameter D increases, so does the difference in length between a wire connecting a needle located at the center of the card 5′ to the associated contact 11 and a wire connecting a needle at the edge of the card 5′ to the associated contact 11. As this difference increases, the differences in resistance and capacitance among the wires increase in proportion. Further, the longer the wires, the higher the probability of crosstalk among the wires.
Moreover, the larger the diameter D, the more likely the probe card 5′ will warp. If the card 5′ warps, the contact resistances between the chip pads on the one hand and the probe needles on the other will become different, and so will become the contact resistances between the probe needles on the one hand and the tester on the other hand. As the probe card 5′ warps, a stress is exerted on the wires provided in the card 5′. Each wire may have its electrical characteristics altered at that part on which an excessive stress is applied.
Any or some of the problems described above impair the accuracy of the probing test achieved by the probe card 5′. Due to theses problems, some of the chips simultaneously tested may be determined to be defective though they are actually flawless, particularly when the tester compares the levels, leading edges and trailing edges of the response signals from the chips with the prescribed values or ranges. In other words, the difference in resistance and capacitance among the wires provided in the card 5′, the difference in pad-needle contact resistance, the difference in needle-tester contact resistance, the changes in the electrical characteristics of the wires, and the crosstalk among the wires prevent the tester from detecting the true characteristics of the chips tested at the same time.
This deterioration of probing-test accuracy is particularly prominent in the test of semiconductor memories having a large storage capacity. This is because these memories operate at so high a speed that only a little allowance is provided for the shifting of the leading and trailing edge time of each signal.
A semiconductor memory having a large storage capacity is one of the most delicate and sensitive devices. Its operation will be jeopardized if even a very small error is made. To see whether such a small error occurs or not, the memory is subjected to proving test which is performed by using a probe card under strict conditions. Therefore, a problem with the wires provided in the probe card lower the test accuracy, even if the problem is a very small one.